Non-volatile memory device with enlarged trapping layer

ABSTRACT

Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to non-volatile memory devices and,more particularly, to non-volatile memory devices having two bits percell.

[0003] 2. Description of Related Art

[0004] A non-volatile semiconductor memory device is designed tomaintain programmed information even in the absence of provided power.The read-only memory (ROM) is a non-volatile memory device commonly usedin electronic equipment such as microprocessor-based digital electronicequipment and portable electronic devices such as cellular phones.

[0005] ROM devices are conventionally arranged into a plurality ofmemory cell arrays. Each memory cell includes a transistor, whichtypically comprises a metal-oxide-semiconductor field effect transistor(MOSFETs) that is juxtaposed between two intersecting bit lines and aword line. Data bit values or codes held by these memory celltransistors are permanently stored (until deliberate erasure) in thephysical or electrical properties of the individual memory cells.Generally speaking, a consequence of the non-volatile nature of a ROM isthat data stored in the memory device can only be read.

[0006] A relatively recent development in non volatile memory has beenthe advent of Nitride-Read Only Memory (NROM) devices. NROM devicesoffer a number of advantages over the 30 year old currently dominantfloating gate devices such as EPROM, Flash, and EEPROM, which storecharge in a conductive floating gate.

[0007] NROM cells can comprise 2 bit flash cells based on charge storagein an Oxide-Nitride-Oxide (ONO) dielectric. The NROM cell may comprisean n-channel MOSFET device wherein nitride is used as a trappingmaterial between a top and bottom oxide. The ONO structure replaces thegate dielectric that is used in floating gate devices. The top andbottom oxide layers should be thicker than 50 A to prevent any oxidedamaging direct electron tunneling during programming.

[0008] NROM flash blocks may be added to standard CMOS processes bylaying down the ONO layer after the field isolation but before the gateoxidation. Adding the NROM components typically has minimal effects onthe CMOS thermal budgets. The NROM memory cells can be programmed bychannel hot electron (CHE) injection, and erased by tunneling enhancedhot hole (TEHH) injection through the bottom oxide. The NROM cellsoperate as localized charge storage devices, which allows the trappedcharge to remain only at the injection point. Thus, single bit failurescommonly experienced by floating gate technologies may be reduced. Thisreduction may allow for further minimization of device size andincreased device density without degradation in performance.

[0009] NROM devices can offer a number of significant advantages overfloating gate devices. Both the bit-size and the die size can be afactor of 3 or more smaller for NROM devices. NROM devices can alsorequire 6 to 8 fewer photomask steps, their process complexity can besimpler, and it can be easier to integrate them with CMOS devices forembedded applications. Furthermore, NROM devices can be more suited tolow voltage product implementation due to a lower erased thresholdvoltage. However, a common problem with NROM devices can be the lateralleakage of trapped charge over the ONO layer edge. Another problem thatmay occur with manufacturing memory devices having critical dimensions(CD) below around 0.15 μm, is a failure to properly resolve the devicegeometries when undergoing photolithographic processing.

SUMMARY OF THE INVENTION

[0010] The present invention relates to nonvolatile memory devices andmethods of forming such nonvolatile memory devices. More particularlythe invention herein provides improved methods of manufacturing NROMmemory devices. The improved processing methods may reduce theoccurrence of electron leakage from the trapped charge in the nitridelayer during high stress operation conditions such as high voltageand/or high temperature. Such leakage may occur at the ONO layer edge.However, forming an ONO stack that has a larger area than the gatestructure (i.e., the portion of a word line between two bit lines) andwhich overlaps the adjoining bit lines in accordance with the presentinvention, can attenuate or eliminate this problem. The invention alsoprovides a dielectric resolution enhancement coating technique toovercome photolithography limitations of patterning the ONO stack belowdimensions around 0.15 μm. Using a dielectric resolution enhancementcoating technique in accordance with the present invention can allow fordevice dimensions which are smaller than the wavelength of the UVradiation used to pattern the photoresist and create the devices.

[0011] In accordance with an aspect of the present invention, a methodfor forming at least one nonvolatile memory device can comprise thesteps of: (a) forming a trapping layer on a prepared semiconductorsubstrate; (b) forming a patterned photoresist layer on the trappinglayer; (c) using the photoresist layer as an implanting mask to performan implantation to form at least one bit line; (d) forming a firstpolymer layer on surfaces of the photoresist layer; (e) using the firstpolymer layer as an etching mask to pattern the trapping layer into atleast one trapping layer strip; (f) removing the first polymer and thephotoresist layer; (g) forming an oxide beside the at least one trappinglayer strip and above the at least one bit line; (h) forming at leastone word line on the at least one trapping layer strip; (h) forming asecond polymer layer on surfaces of the at least one word line; (i)using the second polymer layer as an etching mask to pattern the atleast one trapping layer strip into a plurality of trapping layerblocks; and (j) removing the second polymer.

[0012] The trapping layer may comprise in sequence a first oxide layer,a nitride layer, and a second oxide layer, wherein the first oxidelayer, nitride layer, and second oxide layer form an ONO stack. The ONOstack may be patterned such that the first oxide layer remainssubstantially unpatterned. A BARC may be deposited prior to theapplication of the photoresist layer. The at least one bit line maycomprise a plurality of bit lines, the at least one trapping layer stripmay comprise a plurality of trapping layer strips, and the at least oneword line may comprise a plurality of word lines.

[0013] In accordance with another aspect of the present invention, amethod for forming a nonvolatile memory on a semiconductor substrate cancomprise the steps of (a) providing a prepared semiconductor substrate;(b) forming a trapping layer on the semiconductor substrate; (c)applying and patterning a photoresist over the trapping layer to form aplurality of photoresist strips; (d) selectively implanting thesemiconductor substrate to form a plurality of bit lines; (e) forming afirst polymer on the surfaces of the patterned photoresist; (f) forminga plurality of trapping layer strips by etching back portions of thetrapping layer; (g) removing the first polymer and the patternedphotoresist; (h) forming an oxide over the plurality of bit lines; (i)forming a plurality of word lines; (j) forming a second polymer over theword lines; (k) etching portions of the plurality of trapping layerstrips to form a plurality of trapping layer block structures; and (l)removing the second polymer.

[0014] The trapping layer may comprise in sequence a first oxide layer,a nitride layer, and a second oxide layer, the first oxide layer,nitride layer, and second oxide layer forming an ONO stack. The secondoxide layer formed in the foregoing method may consume some portion ofthe nitride layer during its growth. The etch performed in step (f) mayremove portions of the second oxide layer and the nitride layer, and mayremove a relatively small portion of the first oxide layer. The firstpolymer and second polymer can be formed using a dielectric resolutionenhancement coating technique, which may be performed in an etcher. Thefirst polymer and second polymer may be used as etch masks to protectthe underlying layers during etch processing. The word lines arepreferably centrally disposed over corresponding members of theplurality of trapping layer block structures, the plurality of trappinglayer block structures overlap portions of adjoining members of theplurality of bit lines, and the trapping layer block structures havegreater widths than the corresponding word lines.

[0015] In accordance with one aspect of the present invention, anonvolatile memory device comprises a prepared semiconductor substratein which a plurality of bit lines are implanted. A plurality of trappinglayer block structures form rows and columns, and a plurality of wordlines are positioned over corresponding members of the plurality oftrapping layer block structures. A dielectric is disposed between theplurality of word lines and trapping layer block structures.

[0016] According to another aspect of the invention, a plurality oftrapping layer block structures can overlap portions of adjoiningmembers of the plurality of bit lines, and may be wider than members ofthe plurality of word lines. The word lines may be centrally disposedabove corresponding members of the plurality of trapping layer blockstructures.

[0017] Any feature or combination of features described herein areincluded within the scope of the present invention provided that thefeatures included in any such combination are not mutually inconsistentas will be apparent from the context, this specification, and theknowledge of one of ordinary skill in the art. Additional advantages andaspects of the present invention are apparent in the following detaileddescription and claims.

BRIEF DESCTIPTION OF THE DRAWINGS

[0018]FIG. 1 is a plan view of an NROM semiconductor device after theformation of word lines and bit lines;

[0019]FIG. 2 is a cross-sectional view of an NROM semiconductor devicein an intermediate processing step;

[0020]FIG. 3 is the cross-sectional view of FIG. 2 after a subsequentimplant step;

[0021]FIG. 4 is the cross-sectional view of FIG. 3 with the addition ofa polymer;

[0022]FIG. 5 is the cross-sectional view of FIG. 4 after a subsequentetch process step;

[0023]FIG. 6a is the cross-sectional view of FIG. 5 after allphotoresist has been removed;

[0024]FIG. 6b is a perspective view showing an NROM device at the sameprocessing stage as shown in FIG. 6a;

[0025]FIG. 7 is a cross-sectional view of an NROM device after growingof an oxide;

[0026]FIG. 8 is a cross-sectional view of an NROM device cutorthogonally to FIGS. 2 through 6 in an intermediate processing step;

[0027]FIG. 9 is a cross-sectional view of the NROM device in FIG. 8after a subsequent etch process step;

[0028]FIG. 10 is a cross-sectional view of the NROM device in FIG. 9after the removal of a polymer layer;

[0029]FIG. 11 is a perspective view of an NROM device at the sameprocessing step as FIG. 10; and

[0030]FIG. 12 is a plan view of an NROM device in an intermediateprocessing step showing ON block structures in phantom.

DETAILED DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS

[0031] Reference will now be made in detail to the presently preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same or similar referencenumbers are used in the drawings and the description to refer to thesame or like parts. It should be noted that the drawings are insimplified form and are not to precise scale. In reference to thedisclosure herein, for purposes of convenience and clarity only,directional terms, such as, top, bottom, left, right, up, down, over,above, below, beneath, rear, and front, are used with respect to theaccompanying drawings. Such directional terms should not be construed tolimit the scope of the invention in any manner.

[0032] Although the disclosure herein refers to certain illustratedembodiments, it is to be understood that these embodiments are presentedby way of example and not by way of limitation. The intent of thefollowing detailed description, although discussing exemplaryembodiments, is to be construed to cover all modifications,alternatives, and equivalents of the embodiments as may fall within thespirit and scope of the invention as defined by the appended claims. Forexample, it is understood by a person of ordinary skill practicing thisinvention that NROM device technology can be used to replace thefloating gate technologies of nonvolatile memory devices such as EPROM,Flash, and EEPROM with their NROM counterparts.

[0033] It is to be understood and appreciated that the process steps andstructures described herein do not cover a complete process flow for themanufacture of NROM memory devices. The present invention may bepracticed in conjunction with various integrated circuit fabricationtechniques that are conventionally used in the art, and only so much ofthe commonly practiced process steps are included herein as arenecessary to provide an understanding of the present invention.

[0034] Referring more particularly to the drawings, FIG. 1 illustrates aplan view of a plurality of bit lines 15 orthogonally disposed relativeto a plurality of word lines 17. The plurality of bit lines 15 andplurality of word lines 17 may be fabricated on a semiconductorsubstrate (e.g., doped silicon) alongside customary complementary metaloxide semiconductor (CMOS) devices on the same chip or die. Standardinitial CMOS processes are used to prepare the substrate for theapplication of NROM cells, including for example, field oxidation andwell implant steps.

[0035] A portion of line A-A′ 19, extending orthogonally to theplurality of bit lines 15 over a region not defined by one of theplurality of word lines 17, corresponds to the zoomed in cross-sectionalviews of FIGS. 2 through 6. Likewise, a portion of line B-B′ 21,extending orthogonally relative to the plurality of word lines 17 over aregion not defined by one of the plurality of bit lines 15, correspondsto the zoomed in cross-sectional views of FIGS. 8 through 10 and FIG.12.

[0036] Referring now to FIG. 2, a trapping layer, which preferablycomprises a first oxide layer 26, a nitride layer 28, and a second oxidelayer 30 has been deposited and/or grown over a prepared substrate 24.The first oxide layer 26 and the second oxide layer 30 should be thickenough to prevent the occurrence of electron tunneling between trappedelectrons in the nitride layer 28 and one of the plurality of bit lines15 or plurality of word lines 17, which may occur at thicknesses belowaround 50 angstroms (A). Preferably, the first oxide layer 26 is grownor deposited to a thickness of about 50 to 100 A, the nitride layer 28is deposited to a thickness of between about 35 and 75 A, and the secondoxide layer 30 is grown or deposited to a thickness of about 50 to 150A.

[0037] If the second oxide layer 30 is grown over the nitride layer 28rather than deposited, then some portion of the nitride layer 28 isconsumed in the formation of the oxide at approximately the rate of 1 Aof nitride consumed to 2 A of oxide formed. Thus, the nitride layer 28must be deposited to the desired thickness of 35 to 75 A plus half thedesired thickness of the second oxide layer 30. For example, if it isdesired for the second oxide layer 30 to have a thickness of 150 A, andfor the nitride layer 28 to have a thickness of 50 A, then the nitridelayer 28 must initially be deposited to a thickness of 125 A (50A+75A).

[0038] The first oxide layer 26, nitride layer 28, and second oxidelayer 30 define an oxide-nitride-oxide (ONO) stack 31. The ONO stack 31acts to trap charge within the nitride layer 28, which is electricallyisolated by the second oxide layer 30 and the first oxide layer 26.

[0039] A bottom anti reflective coating (BARC) 32 is deposited followedby the application of a photoresist layer 34, which may be eitherpositive or negative photoresist. The photoresist layer 34 is patternedand developed using common photolithographic processes, forming apattern of photoresist bars extending perpendicularly into the page, asshown in FIG. 2. As in FIG. 3, a dopant 37 such as arsenic orphosphorous is introduced into the exposed portions of the preparedsubstrate 24 by ion implantation to form source and drain regions, or aplurality bit lines 15. The implantation occurs through the ONO stack31, which may prevent the occurrence of ion channeling by providing asurface to implant through that does-not follow the lattice structure ofthe underlying substrate.

[0040] Proceeding to FIG. 4, a first polymer 41 is formed on thesurfaces of the photoresist layer 34 with a dielectric resolutionenhancement coating technique that is performed for example in anetcher, such that the first polymer 41 extends over portions of one ormore of a plurality of bit lines 15. In the illustrated embodiment, thefirst polymer 41 is deposited using a low-temperature (i.e., below about110 degrees C.) plasma-enhanced chemical vapor deposition (PECVD) methodat a pressure of about 1 mT to about 100 mT; a source power of about 500W to about 2000 W; a bias power of about 0 W to about 1100 W; and usinga C₄F₈/CH₂F₂/CHF₃/C₄F₆/C₅F₈/CO/Ar mixture. The first polymer 41 thenperforms the function of an etching mask, preventing the underlyinglayers from being removed during the subsequent etch back of the secondoxide layer 30 and nitride layer 28. As illustrated in FIG. 5, exposedregions of the second oxide layer 30 and nitride layer 28 are completelyremoved by the etch process, leaving an exposed first oxide layer 26.

[0041] In the configuration of FIG. 6a, the first polymer 41,photoresist layer 34, and BARC 32 have been removed by standard stripand ash procedures. Thus, the ONO stack is patterned to form a pluralityof oxide-nitride (ON) strips 43 over the first oxide layer 26, whereineach of the plurality of ON strips 43 lies between two adjacent bitlines, and wherein each of the openings is self-aligned with one of theplurality of bit lines 15. FIG. 6b illustrates a perspective view of thewafer shown in FIG. 6a. As evidenced by the drawing, a plurality of ONstrips 43 lies in a staggered formation relative to a plurality of bitlines 15 (shown in phantom), such that an overlap occurs betweenadjacent members of the plurality of bit lines 15 and the plurality ofON strips 43. In FIG. 7, a thermal oxidation process is implemented togrow exposed surfaces of the first oxide layer 26 in the bit linedirection. As presently embodied, the first oxide layer 26 is grownbetween the trapping layer strips until a height of the first oxidelayer 26 is about equal to a height of the ON strip is 43.

[0042] In the cross-sectional view of the NROM device of FIG. 8, whichis taken along the line B-B′ 21 of FIG. 1, a layer of polysilicon hasbeen deposited over the existing structures and formed into a pluralityof word lines 46. Regarding this formation, a photoresist is applied,patterned, and developed using standard photolithographic techniques, toform a plurality of elongate photoresist structures. The elongatephotoresist structures are used to facilitate the etching of the layerof polysilicion to form a plurality of elongate gate or word linestructures 46. The word line structures 46 are disposed abovecorresponding members of the plurality of ON strips 43. Subsequently, asecond polymer 48 is formed only on the surfaces of the plurality ofword line structures 46, using the above-described dielectric resolutionenhancement coating technique.

[0043] Referring now to FIG. 9, the second polymer 48 functions as anetching mask for patterning the plurality of ON strips 43 into aplurality of ON block structures 54. Each of the plurality of word linestructures 46 is preferably centrally disposed above, and has a widthsmaller than, a corresponding member of the plurality of ON blockstructures 54. Thereafter, the second polymer 48 is removed by a dry orwet etch procedure, the resultant structures of which are illustrated inFIG. 10.

[0044] Other methods for forming an ON block structure that has a largerarea than the gate structure (i.e., the part of a word line between twobit lines) are also possible. For example, it may be possible to includean additional step of adding a photoresist and patterning it so that itexhibits the proper dimensions in place of both the first polymer andsecond polymer steps. The ON layer would then be etched to the desireddimensions according to the dimensions of the above lying photoresistlayers.

[0045] A plan view of the NROM device of FIG. 11 is illustrated in FIG.12. The plurality of ON block structures 54 (shown in phantom) arepreferably disposed directly beneath the plurality of word linestructures 46. As elucidated by the drawing, the plurality of ON blockstructures 54 are wider than members of the plurality of word linestructures 46, and overlap adjoining members of the plurality of bitlines 15.

[0046] In accordance with the present invention, since the ON blockstructures 54 are wider than the word line structures 46, and overlapportions of the adjoining buried drain regions (plurality of bit lines15), the leakage problem associated with current NROM technologies maybe attenuated or avoided. In view of the foregoing, it will beunderstood by those skilled in the art that the methods of the presentinvention can facilitate formation of operational NROM memory devices inintegrated circuits. The above-described embodiments have been providedby way of example, and the present invention is not limited to theseexamples. Multiple variations and modification to the disclosedembodiments will occur, to the extent not mutually exclusive, to thoseskilled in the art upon consideration of the foregoing description. Suchvariations and modifications, however, fall well within the scope of thepresent invention as set forth in the following claims.

What is claimed is:
 1. A method for forming at least one nonvolatilememory device, comprising the following steps: (a) forming a trappinglayer on a prepared substrate; (b) forming a patterned photoresist layeron the trapping layer; (c) using the photoresist layer as an implantingmask to perform an implantation to form at least one bit line; (d)forming a first material layer on surfaces of the photoresist layer; (e)using the first material layer as an etching mask to pattern thetrapping layer into at least one trapping layer strip; (f) removing thefirst material and the photoresist layer; (g) forming an oxide besidethe at least one trapping layer strip and above the at least one bitline; (h) forming at least one word line on the at least one trappinglayer strip; (i) forming a second material layer on surfaces of the atleast one word line; (j) using the second material layer as an etchingmask to pattern the at least one trapping layer strip into a pluralityof trapping layer block structures; and (k) removing the second polymer.2. The method of claim 1, wherein the first material layer comprises afirst polymer and the second material layer comprises a second polymer.3. The method of claim 2, wherein the trapping layer comprises insequence, a first oxide layer, a nitride layer, and a second oxidelayer, the first oxide layer, nitride layer, and second oxide layerforming an oxide-nitride-oxide (ONO) stack.
 4. The method of claim 3,wherein the step of patterning the trapping layer comprises patterningthe oxide-nitride layer of the ONO stack only so that the first oxidelayer remains substantially unpatterned.
 5. The method of claim 2,further comprising a step of forming a BARC layer before the photoresistlayer is formed.
 6. The method of claim 2, wherein: the at least one bitline comprises a plurality of bit lines; the at least one trapping layerstrip comprises a plurality of trapping layer strips; and the at leastone word line comprises a plurality of word lines.
 7. The method ofclaim 6, wherein: the trapping layer comprises an oxide-nitride-oxide(ONO) film; and the step of patterning the trapping layer comprisespatterning the oxide-nitride layer of the ONO stack only so that thefirst oxide layer remains substantially unpatterned.
 8. A method forforming a nonvolatile memory on a semiconductor substrate, the methodcomprising the steps of: (a) providing a prepared semiconductorsubstrate; (b) forming a trapping layer on the semiconductor substrate;(c) applying and patterning a photoresist over the trapping layer toform a plurality of photoresist strips; (d) selectively implanting thesemiconductor substrate to form a plurality of bit lines; (e) forming afirst material layer on surfaces of the patterned photoresist; (f)etching back portions of the trapping layer to form a plurality oftrapping layer strips; (g) removing the first material layer and thepatterned photoresist; (h) forming an oxide over the plurality of bitlines; (i) forming a plurality of word lines; (j) forming a secondmaterial layer on surfaces of the word lines; (k) etching portions ofthe plurality of trapping layer strips to form a plurality of trappinglayer block structures; and (l) removing the second material layer. 9.The method of claim 8, wherein the first material layer comprises afirst polymer and the second material layer comprises a second polymer.10. The method of claim 9, wherein the step of forming an oxidecomprises a step of growing an oxide between the trapping layer stripsuntil a height of the oxide is about equal to a height of the trappinglayer strips.
 11. The method of claim 9, wherein the trapping layercomprises in sequence, a first oxide layer, a nitride layer, and asecond oxide layer, the first oxide layer, nitride layer, and secondoxide layer forming an oxide-nitride-oxide (ONO) stack.
 12. The methodof claim 11, wherein the second oxide layer is grown over the nitridelayer, and wherein the second oxide layer consumes a portion of thenitride layer during the growth.
 13. The method of claim 11, wherein theetch performed in step (f) removes portions of the second oxide layerand the nitride layer only.
 14. The method of claim 11, wherein the etchperformed in step (f) removes portions of the second oxide layer andportions of the nitride layer, and further removes smaller portions ofthe first oxide layer, the portions being substantially greater than thesmaller portions.
 15. The method of claim 9, wherein the first polymerand the second polymer are formed using a dielectric resolutionenhancement coating technique.
 16. The method of claim 15, wherein thedielectric resolution enhancement coating technique is performed in anetcher.
 17. The method of claim 9, wherein the first polymer layer isused as an etch block during the etch of step (f).
 18. The method ofclaim 9, wherein the second polymer layer is used as an etch blockduring the etch of step (k).
 19. The method of claim 9, wherein theplurality of word lines are centrally disposed above correspondingmembers of the plurality of trapping layer block structures.
 20. Themethod of claim 9, wherein each trapping layer block structure overlapsportions of adjoining bit lines of the plurality of bit lines.
 21. Themethod of claim 9, wherein each trapping layer block structure has agreater width than a corresponding word line.
 22. A nonvolatile memoryon a semiconductor substrate, comprising: (a) a prepared semiconductorsubstrate; (b) a plurality of bit lines; (c) a plurality of trappinglayer block structures; and (d) a plurality of word lines overcorresponding members of the plurality of trapping layer blockstructures, wherein widths of the trapping layer block structures aregreater than widths of the word lines.
 23. The nonvolatile memory ofclaim 22, and further comprising at least one dielectric disposedbetween the plurality of word lines and trapping layer block structures.24. The nonvolatile memory of claim 22, wherein the plurality oftrapping layer block structures comprises in sequence, a first oxidelayer, a nitride layer, and a second oxide layer.
 25. The nonvolatilememory of claim 22, wherein the plurality of trapping layer blockstructures overlaps portions of adjoining members of the plurality ofbit lines.